60 search results - page 8 / 12 » An Issue Logic for Superscalar Microprocessors |
ARCS
2010
Springer
14 years 6 days ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
SC
2005
ACM
14 years 28 days ago
2005
ACM
The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end computing (HEC) platforms, primarily because of their generality, ...
ISCA
2002
IEEE
14 years 9 days ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
APCSAC
2001
IEEE
13 years 11 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
EUROPAR
2001
Springer
13 years 12 months ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...