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» An Optical Simulation of Shared Memory
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CF
2010
ACM
14 years 15 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
ICCD
1994
IEEE
85views Hardware» more  ICCD 1994»
13 years 11 months ago
A Superassociative Tagged Cache Coherence Directory
Dynamically tagged directories are memory-efficient mechanisms for maintaining cache coherence in sharedmemory multiprocessors. These directories use specialpurpose caches of poin...
David J. Lilja, Shanthi Ambalavanan
DC
2010
13 years 7 months ago
Model checking transactional memories
Model checking software transactional memories (STMs) is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memo...
Rachid Guerraoui, Thomas A. Henzinger, Vasu Singh
IPPS
2007
IEEE
14 years 1 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
PADS
2005
ACM
14 years 29 days ago
Seven-O'Clock: A New Distributed GVT Algorithm Using Network Atomic Operations
In this paper we introduce a new concept, network atomic operations (NAOs) to create a zero-cost consistent cut. Using NAOs, we define a wall-clock-time driven GVT algorithm call...
David W. Bauer, Garrett R. Yaun, Christopher D. Ca...