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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 4 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
TSP
2008
118views more  TSP 2008»
15 years 7 months ago
Channel-Aware Random Access Control for Distributed Estimation in Sensor Networks
A cross-layered slotted ALOHA protocol is proposed and analyzed for distributed estimation in sensor networks. Suppose that the sensors in the network record local measurements of ...
Y.-W. P. Hong, Keng-U Lei, Chong-Yung Chi
220
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LCTRTS
2010
Springer
16 years 2 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
BIOINFORMATICS
2005
152views more  BIOINFORMATICS 2005»
15 years 7 months ago
Intervention in context-sensitive probabilistic Boolean networks
Motivation: Intervention in a gene regulatory network is used to help it avoid undesirable states, such as those associated with a disease. Several types of intervention have been...
Ranadip Pal, Aniruddha Datta, Michael L. Bittner, ...
202
Voted
IPPS
2003
IEEE
16 years 22 days ago
Parallel ROLAP Data Cube Construction On Shared-Nothing Multiprocessors
The pre-computation of data cubes is critical to improving the response time of On-Line Analytical Processing (OLAP) systems and can be instrumental in accelerating data mining tas...
Ying Chen, Frank K. H. A. Dehne, Todd Eavis, Andre...