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» An algorithm for minimizing the Mumford-Shah functional
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GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach
FPGA
1997
ACM
120views FPGA» more  FPGA 1997»
14 years 26 days ago
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping
In this paper, we give a necessary and sufficient condition for the existence of partially-dependent functional decomposition and develop new algorithms to compute such decomposi...
Jason Cong, Yean-Yow Hwang
ASPDAC
2005
ACM
146views Hardware» more  ASPDAC 2005»
13 years 10 months ago
High-level synthesis for DSP applications using heterogeneous functional units
Abstract— This paper addresses high level synthesis for realtime digital signal processing (DSP) architectures using heterogeneous functional units (FUs). For such special purpos...
Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edw...
ICANN
2005
Springer
14 years 2 months ago
Interpolation Mechanism of Functional Networks
In this paper, the interpolation mechanism of functional networks is discussed. A kind of fourlayer (with 1 input and 1 output unit) and a five-layer (with double input and single...
Yong-Quan Zhou, Licheng Jiao
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 5 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky