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EUROPAR
2010
Springer
13 years 8 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
ECRTS
2008
IEEE
14 years 1 months ago
WCET-driven Cache-based Procedure Positioning Optimizations
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...
Paul Lokuciejewski, Heiko Falk, Peter Marwedel
ECRTS
2009
IEEE
13 years 5 months ago
Using Randomized Caches in Probabilistic Real-Time Systems
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
Eduardo Quiñones, Emery D. Berger, Guillem ...
WSC
1998
13 years 8 months ago
A Speculation-based Approach for Performance and Dependability Analysis: A Case Study
In this paper, we propose two speculation-based methods for fast and accurate simulation-based performance and dependability analysis of complex systems, incorporating detailed si...
Yiqing Huang, Zbigniew Kalbarczyk, Ravishankar K. ...
CSREAESA
2003
13 years 9 months ago
Static Pattern Predictor (SPP) Based Low Power Instruction Cache Design
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
Kugan Vivekanandarajah, Thambipillai Srikanthan, C...