75 search results - page 14 / 15 » An efficient approach to simultaneous transistor and interco... |
DAC
2000
ACM
14 years 10 months ago
2000
ACM
eously demand shorter and less costly design cycles. Designing at higher levels of abstraction makes both objectives achievable, but enabling techniques like behavioral synthesis h...
JETC
2008
13 years 7 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
SIGOPS
2010
13 years 3 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
ECCV
2006
Springer
14 years 11 months ago
2006
Springer
One main challenge in Augmented Reality (AR) applications is to keep track of video objects with their movement, orientation, size, and position accurately. This poses a challengin...