Sciweavers

102 search results - page 18 / 21
» An efficient parallel termination detection algorithm
Sort
View
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
14 years 1 months ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
COMPUTING
1999
99views more  COMPUTING 1999»
13 years 7 months ago
A Minimal Line Property Preserving Representation of Line Images
In line image understandingaminimal lineproperty preserving(MLPP)graphoftheimagecompliments the structural information in geometric graph representations like the run graph. With ...
Mark Burge, Walter G. Kropatsch
POPL
2010
ACM
14 years 5 months ago
A simple, verified validator for software pipelining
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
Jean-Baptiste Tristan, Xavier Leroy
AIPR
2008
IEEE
13 years 9 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
NETWORKING
2010
13 years 9 months ago
Bidirectional Range Extension for TCAM-Based Packet Classification
Abstract. Packet classification is a fundamental task for network devices such as edge routers, firewalls, and intrusion detection systems. Currently, most vendors use Ternary Cont...
Yan Sun, Min Sik Kim