16 search results - page 3 / 4 » An embedded DRAM architecture for large-scale spatial-lattic... |
ICDCS
2011
IEEE
12 years 6 months ago
2011
IEEE
—Massively parallel scientific applications, running on extreme-scale supercomputers, produce hundreds of terabytes of data per run, driving the need for storage solutions to im...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
IMC
2003
ACM
14 years 7 days ago
2003
ACM
Internet coordinate schemes have been proposed as a method for estimating minimum round trip time between hosts without direct measurement. In such a scheme, each host is assigned...
JPDC
2007
13 years 6 months ago
2007
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...