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ISCAS
2005
IEEE
155views Hardware» more  ISCAS 2005»
14 years 28 days ago
Hyperblock formation: a power/energy perspective for high performance VLIW architectures
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
ICIP
2000
IEEE
14 years 9 months ago
Performance Analysis of an H.263 Video Encoder for VIRAM
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
Thinh P. Q. Nguyen, Avideh Zakhor, Katherine A. Ye...
CSREAESA
2010
13 years 5 months ago
Customizable and Predictable Synchronization in a Component-Based OS
Component-based operating systems enable embedded systems to adapt system policies, mechanisms, and abstractions to the specific workloads and contexts of each system. The scope o...
Gabriel Parmer, Jiguo Song
RTCSA
2007
IEEE
14 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
SIGOPS
2008
152views more  SIGOPS 2008»
13 years 7 months ago
The Caernarvon secure embedded operating system
The Caernarvon operating system was developed to demonstrate that a high assurance system for smart cards was technically feasible and commercially viable. The entire system has b...
David C. Toll, Paul A. Karger, Elaine R. Palmer, S...