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» An improvement in formal verification
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FDL
2007
IEEE
14 years 1 months ago
Transactor-based Formal Verification of Real-time Embedded Systems
With the increasing complexity of today's embedded systems, there is a need to formally verify such designs at mixed abstraction levels. This is needed if some compoe describ...
Daniel Karlsson, Petru Eles, Zebo Peng
FM
2006
Springer
134views Formal Methods» more  FM 2006»
14 years 1 months ago
Formal Verification of a C Compiler Front-End
This paper presents the formal verification of a compiler front-end that translates a subset of the C language into the Cminor intermediate language. The semantics of the source an...
Sandrine Blazy, Zaynah Dargaye, Xavier Leroy
FMICS
2008
Springer
13 years 11 months ago
Formal Verification of the Implementability of Timing Requirements
There has been relatively little work on the implementability of timing requirements. We have previously provided definitions of fundamental timing operators that explicitly consid...
Xiayong Hu, Mark Lawford, Alan Wassyng
FLAIRS
2000
13 years 11 months ago
Verification of Cooperating Systems - An Approach Based on Formal Languages
Behaviour of systems is described by formal languages: the sets of all sequences of actions. Regarding ion, alphabetic language homomorphisms are compute abstract behaviours. To a...
Peter Ochsenschläger, Jürgen Repp, Rolan...
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
14 years 1 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...