Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less...
This paper describes formal modeling and verification of automation systems from the system engineering point of view. Reuse of model components is the key issue in order to bring...
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
We describe a formal verification of a recent concurrent list-based set algorithm due to Heller et al. The algorithm is optimistic: the add and remove operations traverse the list ...
Robert Colvin, Lindsay Groves, Victor Luchangco, M...
In this paper, formal verification methodologies and the SPR (Safety Problem Resolver) model checking tool are used for verifying a security model's safety. The SPR tool makes...
Il-Gon Kim, Miyoung Kang, Jin-Young Choi, Peter D....