We present the logic CTL.STIT, which is the join of the logic CTL with a multi-agent strategic stit-logic variant. CTL.STIT subsumes ATL, and adds expressivity to it that we claim...
This paper examines the suitability and use of runtime verification as means for monitoring security protocols and their properties. In particular, we employ the runtime verificat...
We present a framework for formal verification of embedded custom memories. Memory verification is complicated ifficulty in abstracting design parameters induced by the inherently ...
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
Biniam Gebremichael, Frits W. Vaandrager, Miaomiao...
This paper presents a formal approach based on the RTLOTOS formal description technique for the semantic verification of SMIL documents. The reachability analysis of RT-LOTOS spec...
Paulo Nazareno Maia Sampaio, C. A. S. Santos, Jean...