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» An improvement in formal verification
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ENTCS
2006
131views more  ENTCS 2006»
13 years 9 months ago
The Case for Analog Circuit Verification
The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases...
Chris J. Myers, Reid R. Harrison, David Walter, Ni...
ISSTA
1998
ACM
14 years 1 months ago
Improving Efficiency of Symbolic Model Checking for State-Based System Requirements
We present various techniques for improving the time and space efficiency of symbolic model checking for system requirements specified as synchronous finite state machines. We use...
William Chan, Richard J. Anderson, Paul Beame, Dav...
CORR
2010
Springer
176views Education» more  CORR 2010»
13 years 10 months ago
Bus Protocols: MSC-Based Specifications and Translation into Program of Verification Tool for Formal Verification
Message Sequence Charts (MSCs) are an appealing visual formalism mainly used in the early stages of system design to capture the system requirements. However, if we move towards a...
Kamrul Hasan Talukder
FMCAD
2006
Springer
14 years 1 months ago
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
Tilman Glökler, Jason Baumgartner, Devi Shanm...