423 search results - page 37 / 85 » An integrated model for logistics network design |
ISPD
2006
ACM
14 years 2 months ago
2006
ACM
In this paper, we propose more accurate power/ground network circuit model, which consider both via and ground bounce effects to improve the performance estimation accuracy of on-...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
FPGA
2006
ACM
14 years 12 days ago
2006
ACM
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
SIGCOMM
2010
ACM
13 years 9 months ago
2010
ACM
Security functions such as access control, encryption and authentication are typically left up to applications on the modern Internet. There is no unified system to implement thes...