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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 1 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an eļ¬ƒcient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
ICS
1999
Tsinghua U.
13 years 12 months ago
Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity
Current high-end parallel systems achieve low-latency, highbandwidth network communication through the use of aggressive design techniques and expensive mechanical and electrical ...
José F. Martínez, Josep Torrellas, J...
AINA
2009
IEEE
14 years 2 months ago
Predictive Simulation of HPC Applications
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...
Simon D. Hammond, J. A. Smith, Gihan R. Mudalige, ...
EUROSYS
2010
ACM
14 years 4 months ago
Reverse Engineering of Binary Device Drivers with RevNIC
This paper presents a technique that helps automate the reverse engineering of device drivers. It takes a closed-source binary driver, automatically reverse engineers the driverā€...
Vitaly Chipounov, George Candea
ISCA
1999
IEEE
105views Hardware» more  ISCA 1999»
13 years 12 months ago
The Program Decision Logic Approach to Predicated Execution
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
David I. August, John W. Sias, Jean-Michel Puiatti...