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JCP
2008
118views more  JCP 2008»
13 years 6 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
ARC
2008
Springer
112views Hardware» more  ARC 2008»
13 years 8 months ago
Optimal Unroll Factor for Reconfigurable Architectures
Abstract. Loops are an important source of optimization. In this paper, we address such optimizations for those cases when loops contain kernels mapped on reconfigurable fabric. We...
Ozana Silvia Dragomir, Elena Moscu Panainte, Koen ...
EUROSYS
2006
ACM
13 years 10 months ago
Context-specific middleware specialization techniques for optimizing software product-line architectures
Product-line architectures (PLA)s are an emerging paradigm for developing software families for distributed real-time and embedded (DRE) systems by customizing reusable artifacts,...
Arvind S. Krishna, Aniruddha S. Gokhale, Douglas C...
ICASSP
2011
IEEE
12 years 10 months ago
A combinatorial optimization framework for subset selection in distributed multiple-radar architectures
Abstract—Widely distributed multiple radar architectures offer parameter estimation improvement for target localization. For a large number of radars, the achievable localization...
Hana Godrich, Athina P. Petropulu, H. Vincent Poor
IPPS
1998
IEEE
13 years 11 months ago
Hyper Butterfly Network: A Scalable Optimally Fault Tolerant Architecture
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...
Wei Shi, Pradip K. Srimani