562 search results - page 32 / 113 » Analysis of Hardware Acceleration in Reconfigurable Embedded... |
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a mechanism for the separation of control and data flow in NoC-based SoCs consisting of multiple heterogeneous reconfigurable IP cores. This mechanism enables ...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
ICPADS
2006
IEEE
14 years 1 months ago
2006
IEEE
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
ICSEA
2006
IEEE
14 years 1 months ago
2006
IEEE
— Currently there are different approaches to develop fault-tolerant embedded software: implementing the system from scratch or using libraries respectively specialized hardware....
SUTC
2008
IEEE
14 years 2 months ago
2008
IEEE
As the robotic industry is growing boomingly, the functionalities and system's architecture of robots are more and more complex. The development of robotic application system...