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DAC
2009
ACM
14 years 5 days ago
Vicis: a reliable network for unreliable silicon
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacc...
HASE
2007
IEEE
14 years 1 months ago
Integrating Product-Line Fault Tree Analysis into AADL Models
Fault Tree Analysis (FTA) is a safety-analysis technique that has been recently extended to accommodate product-line engineering for critical domains. This paper describes a tool-...
Hongyu Sun, Miriam Hauptman, Robyn R. Lutz
WORDS
2005
IEEE
14 years 1 months ago
Virtual Networks in an Integrated Time-Triggered Architecture
Depending on the physical structuring of large distributed safety-critical real-time systems, one can distinguish federated and integrated system architectures. This paper investi...
Roman Obermaisser, Philipp Peti, Hermann Kopetz
JSAC
2006
172views more  JSAC 2006»
13 years 7 months ago
A Memory-Efficient Parallel String Matching Architecture for High-Speed Intrusion Detection
The ability to inspect both packet headers and payloads to identify attack signatures makes network intrusion detection system (NIDS) a promising approach to protect Internet syste...
Hongbin Lu, Kai Zheng, Bin Liu, Xin Zhang, Y. Liu
ECBS
2007
IEEE
118views Hardware» more  ECBS 2007»
13 years 9 months ago
An Event-Driven Architecture for Fine Grained Intrusion Detection and Attack Aftermath Mitigation
In today’s computing environment, unauthorized accesses and misuse of critical data can be catastrophic to personal users, businesses, emergency services, and even national defe...
Jianfeng Peng, Chuan Feng, Haiyan Qiao, Jerzy W. R...