747 search results - page 15 / 150 » Analysis of communication delay bounds for network on chips |
SAC
2006
ACM
14 years 2 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
PODC
2009
ACM
14 years 9 months ago
2009
ACM
d Abstract] Christoph Lenzen Computer Engineering and Networks Laboratory (TIK) ETH Zurich, 8092 Zurich, Switzerland lenzen@tik.ee.ethz.ch Thomas Locher Computer Engineering and N...
FGCN
2007
IEEE
14 years 3 months ago
2007
IEEE
In many applications of sensor networks, it is essential to ensure that messages are transmitted to their destinations as early as possible and the buffer size of each sensor node...
GECCO
2010
Springer
14 years 1 months ago
2010
Springer
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
INFOCOM
2011
IEEE
13 years 12 days ago
2011
IEEE
—Body sensor networks (BSNs) have been developed for a set of performance-critical applications, including smart healthcare, assisted living, emergency response, athletic perform...