98 search results - page 10 / 20 » Analytic Evaluation of Shared-memory Systems with ILP Proces... |
LCTRTS
2007
Springer
14 years 2 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
SASP
2008
IEEE
14 years 2 months ago
2008
IEEE
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
SIGMETRICS
2012
ACM
11 years 11 months ago
2012
ACM
Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbate...
HPCA
1997
IEEE
14 years 24 days ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...