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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 3 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
EMSOFT
2009
Springer
14 years 4 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
12 years 9 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
14 years 1 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
ADVIS
2000
Springer
14 years 2 months ago
Evolutionary Prefetching and Caching in an Independent Storage Units Model
Modern applications demand support for a large number of clients and require large scale storage subsystems. This paper presents a theoretical model of prefetching and caching of s...
Athena Vakali