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DFT
2004
IEEE
78views VLSI» more  DFT 2004»
13 years 11 months ago
Reliability Modeling and Assurance of Clockless Wave Pipeline
This paper presents theoretical yet practical methodologies to model, assure and optimize the Reliability of Clockless Wave Pipeline. Clockless wave pipeline is a cutting-edge and...
T. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lomb...
CF
2006
ACM
13 years 11 months ago
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
Juan del Cuvillo, Weirong Zhu, Guang R. Gao
CF
2006
ACM
13 years 11 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
CIT
2006
Springer
13 years 11 months ago
A new collision resistant hash function based on optimum dimensionality reduction using Walsh-Hadamard transform
Hash functions play the most important role in various cryptologic applications, ranging from data integrity checking to digital signatures. Our goal is to introduce a new hash fu...
Barzan Mozafari, Mohammad Hasan Savoji
FCCM
2004
IEEE
152views VLSI» more  FCCM 2004»
13 years 11 months ago
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
Dynamically Reconfigurable Processor (DRP)[1] developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixte...
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki...
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