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ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
15 years 8 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
107
Voted
PEPM
2007
ACM
15 years 8 months ago
Poly-controlled partial evaluation in practice
Poly-Controlled Partial Evaluation (PCPE) is a powerful approach to partial evaluation, which has recently been proposed. PCPE takes into account sets of control strategies instea...
Claudio Ochoa, Germán Puebla
WIOPT
2006
IEEE
15 years 8 months ago
Connection-level QoS provisioning in multiple transmission technology-based OFDM system
A state-of-the-art orthogonal frequency division multiplexing (OFDM)-based access system, such as the DiffSeg system [1][2], uses a different set of transmission technologies, e.g...
Youngkyu Choi, Sunghyun Choi, Sung-Pil Hong
108
Voted
UIC
2009
Springer
15 years 9 months ago
Printing in Ubiquitous Computing Environments
Document printing has long been considered an indispensable part of the workspace. While this process is considered trivial and simple for environments where resources are ample (e...
Athanasios Karapantelakis, Alisa Devlic, Mohammad ...
DSN
2007
IEEE
15 years 8 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...