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ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 9 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
ICPP
2007
IEEE
14 years 2 months ago
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors
Ever-increasing memory footprint of applications and increasing mainstream popularity of shared memory parallel computing motivate us to explore memory compression potential in di...
Lakshmana Rao Vittanala, Mainak Chaudhuri
IPPS
2006
IEEE
14 years 1 months ago
Automatic application-specific microarchitecture reconfiguration
Applications for constrained embedded systems are subject to strict time constraints and restrictive resource utilization. With soft core processors, application developers can cu...
Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamb...
PPOPP
2009
ACM
14 years 8 months ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...

Publication
248views
13 years 4 months ago
Equalizer: A Scalable Parallel Rendering Framework
Continuing improvements in CPU and GPU performances as well as increasing multi-core processor and cluster-based parallelism demand for flexible and scalable parallel rendering sol...
Stefan Eilemann, Maxim Makhinya, Renato Pajarola