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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
14 years 2 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
PARELEC
2006
IEEE
14 years 2 months ago
Hierarchical Partitioning for Piecewise Linear Algorithms
processor arrays can be used as accelerators for a plenty of data flow-dominant applications. The explosive growth in research and development of massively parallel processor arr...
Hritam Dutta, Frank Hannig, Jürgen Teich
IPPS
2006
IEEE
14 years 2 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
TASLP
2010
113views more  TASLP 2010»
13 years 3 months ago
Spherical Harmonic Analysis of Wavefields Using Multiple Circular Sensor Arrays
Spherical harmonic decomposition of wavefields is not only an active problem in acoustic signal processing but also a useful tool in a plethora of applications such as 3D beamform...
Thushara D. Abhayapala, Aastha Gupta
ERSA
2009
131views Hardware» more  ERSA 2009»
13 years 6 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...