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» Application of Reduce Order Modeling to Time Parallelization
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ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
14 years 2 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
ICPPW
2005
IEEE
14 years 2 months ago
A Practical Approach to the Rating of Barrier Algorithms Using the LogP Model and Open MPI
Large–scale parallel applications performing global synchronization may spend a significant amount of execution time waiting for the completion of a barrier operation. Conseque...
Torsten Hoefler, Lavinio Cerquetti, Torsten Mehlan...
NPL
2006
90views more  NPL 2006»
13 years 9 months ago
Hierarchical Incremental Class Learning with Reduced Pattern Training
Hierarchical Incremental Class Learning (HICL) is a new task decomposition method that addresses the pattern classification problem. HICL is proven to be a good classifier but clos...
Sheng Uei Guan, Chunyu Bao, Ru-Tian Sun
ICPP
2007
IEEE
14 years 3 months ago
Architectural Challenges in Memory-Intensive, Real-Time Image Forming
The real-time image forming in future, high-end synthetic aperture radar systems is an example of an application that puts new demands on computer architectures. The initial quest...
Anders Ahlander, H. Hellsten, K. Lind, J. Lindgren...
SNPD
2008
13 years 10 months ago
An Efficient Parallel Eye Detection Algorithm on Facial Color Images
As processing power becomes cheaper and more available in cluster of computers, the need for parallel algorithm that can harness this computing potentials will increase. One applic...
Jalal A. Nasiri, M. Amir Moulavi, Sepideh Nazemi G...