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» Application of Reduce Order Modeling to Time Parallelization
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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 2 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
TCOM
2010
101views more  TCOM 2010»
13 years 3 months ago
Spectral efficient transmit diversity techniques without cyclic prefix for fading relay channels
Abstract--This paper proposes spectral efficient relayassisted transmit diversity techniques, i.e., space-time and space-frequency block codes (STBC/SFBC), for single carrier frequ...
Ui-Kun Kwon, Dae-Young Seol, Gi-Hong Im
CODES
2010
IEEE
13 years 7 months ago
Statistical approach in a system level methodology to deal with process variation
The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of...
Concepción Sanz Pineda, Manuel Prieto, Jos&...
ASAP
2005
IEEE
165views Hardware» more  ASAP 2005»
14 years 2 months ago
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...
JCO
2010
99views more  JCO 2010»
13 years 7 months ago
Online scheduling with a buffer on related machines
Online scheduling with a buffer is a semi-online problem which is strongly related to the basic online scheduling problem. Jobs arrive one by one and are to be assigned to paralle...
György Dósa, Leah Epstein