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ISLPED
2009
ACM
127views Hardware» more  ISLPED 2009»
14 years 2 months ago
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
In this paper, we observe that minimum energy Emin of subthreshold logic dramatically increases when reaching 45 nm node. We demonstrate by circuit simulation and analytical model...
David Bol, Dina Kamel, Denis Flandre, Jean-Didier ...
ISCAS
2008
IEEE
104views Hardware» more  ISCAS 2008»
14 years 2 months ago
An offset compensation technique for bandgap voltage reference in CMOS technology
— A precision integrated bandgap voltage reference in 0.35μm CMOS technology is here presented. The circuit uses natural npn bipolar transistors as reference diodes. A particula...
Stefano Ruzza, Enrico Dallago, Giuseppe Venchi, Se...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 2 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 2 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier