— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
—This paper presents an analog neuromimetic integrated circuit and an associated system dedicated for experiments of parameters extraction in biological neuron models. The IC bas...
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana...
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...