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DATE
2006
IEEE
85views Hardware» more  DATE 2006»
14 years 2 months ago
Test set enrichment using a probabilistic fault model and the theory of output deviations
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
14 years 2 months ago
Neuromimetic ICs and system for parameters extraction in biological neuron models
—This paper presents an analog neuromimetic integrated circuit and an associated system dedicated for experiments of parameters extraction in biological neuron models. The IC bas...
Sylvain Saïghi, Yannick Bornat, Jean Tomas, S...
ASPDAC
2006
ACM
115views Hardware» more  ASPDAC 2006»
14 years 1 months ago
DraXRouter: global routing in X-Architecture with dynamic resource assignment
In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Archi...
Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hon...
DAC
2006
ACM
14 years 1 months ago
A reconfigurable design-for-debug infrastructure for SoCs
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana...
DAC
2006
ACM
14 years 1 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan