3256 search results - page 107 / 652 » Applications of Formal Methods to System Design and Verifica... |
160
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SIGSOFT
2007
ACM
16 years 5 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
186
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GLVLSI
2002
IEEE
15 years 9 months ago
2002
IEEE
Spectral techniques have found many applications in computeraided design, including synthesis, verification, and testing. Decision diagram representations permit spectral coeffici...
132
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FPL
2006
Springer
15 years 8 months ago
2006
Springer
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
136
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JIRS
2007
15 years 4 months ago
2007
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
159
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DAC
2009
ACM
15 years 8 months ago
2009
ACM
Power grid verification in modern integrated circuits is an integral part of early system design where adjustments can be most easily incorporated. In this work, we describe an ea...