Sciweavers

3256 search results - page 135 / 652
» Applications of Formal Methods to System Design and Verifica...
Sort
View
ASE
2005
103views more  ASE 2005»
15 years 4 months ago
Component Verification with Automatically Generated Assumptions
Abstract. Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. The typical approach to verifying propertie...
Dimitra Giannakopoulou, Corina S. Pasareanu, Howar...
126
Voted
DAC
1997
ACM
15 years 8 months ago
Schedule Validation for Embedded Reactive Real-Time Systems
Task scheduling forreactive real time systems is a di cult problem due to tight constraints that the schedule must satisfy. A static priority scheme is proposed here that can be f...
Felice Balarin, Alberto L. Sangiovanni-Vincentelli
157
Voted
ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
15 years 6 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh
POPL
2009
ACM
16 years 5 months ago
A calculus of atomic actions
We present a proof calculus and method for the static verification of assertions and procedure specifications in shared-memory concurrent programs. The key idea in our approach is...
Tayfun Elmas, Shaz Qadeer, Serdar Tasiran
151
Voted
CADE
2007
Springer
16 years 4 months ago
Solving Quantified Verification Conditions Using Satisfiability Modulo Theories
Abstract. First order logic provides a convenient formalism for describing a wide variety of verification conditions. Two main approaches to checking such conditions are pure first...
Yeting Ge, Clark Barrett, Cesare Tinelli