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ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
13 years 11 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
AAAI
2008
13 years 10 months ago
Factored Models for Probabilistic Modal Logic
Modal logic represents knowledge that agents have about other agents' knowledge. Probabilistic modal logic further captures probabilistic beliefs about probabilistic beliefs....
Afsaneh Shirazi, Eyal Amir
GLVLSI
2006
IEEE
115views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
Song Peng, Rajit Manohar
LOPSTR
1998
Springer
13 years 12 months ago
Inductive Synthesis of Logic Programs by Composition of Combinatory Program Schemes
Based on a variable-free combinatory form of definite clause logic programs we outline a methodology and supporting program environment CombInduce for inducing well-moded logic pro...
Andreas Hamfelt, Jørgen Fischer Nilsson
DEON
2010
Springer
13 years 10 months ago
A Logical Model of Private International Law
We provide a logical analysis of private international law, the body of law establishing when courts of a country should decide a case (jurisdiction) and what legal system they sho...
Phan Minh Dung, Giovanni Sartor