16 search results - page 3 / 4 » Applying Decay to Reduce Dynamic Power in Set-Associative Ca... |
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
ICS
2005
Tsinghua U.
14 years 29 days ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
NOSSDAV
2009
Springer
14 years 2 months ago
2009
Springer
Hard-disk drive power consumption reduction methods focus mainly on increasing the amount of time the disk is in standby mode (disk spun down) by implementing aggressive data read...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...