62 search results - page 5 / 13 » Applying Logic Synthesis for Speeding Up SAT |
CF
2008
ACM
13 years 10 months ago
2008
ACM
Using a new exact synthesizer that automatically induces minimal universal boolean function libraries, we introduce two indicators for comparing their expressiveness: the first ba...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We propose a methodology for applying gate-level logic transformations to optimize power in digital circuits. Statistically simulated[14] switching information, gate delays, signa...
CADE
2001
Springer
14 years 8 months ago
2001
Springer
This paper investigates optimization techniques and data structures exploiting the use of so-called pseudo models. These techniques are applied to speed up TBox and ABox reasoning ...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Boolean Satisfiability is seeing increasing use as a decision procedure in Electronic Design Automation (EDA) and other domains. Most applications encode their domain specific cons...
GLVLSI
2000
IEEE
14 years 11 days ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...