103 search results - page 12 / 21 » Approximate Symbolic Model Checking for Incomplete Designs |
ASYNC
1997
IEEE
13 years 11 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
JSA
2008
13 years 7 months ago
2008
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describ...
MSS
1999
IEEE
13 years 12 months ago
1999
IEEE
Benchmark tests have been designed and conducted for the purpose of evaluating the use of automated tape libraries in on-line digital check image retrieval applications. This type...
CAV
2003
Springer
14 years 24 days ago
2003
Springer
ion and BDDs Complement SAT-based BMC in DiVer Aarti Gupta1, Malay Ganai1 , Chao Wang2, Zijiang Yang1, Pranav Ashar1 1 NEC Laboratories America, Princeton, NJ, U.S.A. 2 University ...
FMICS
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...