111 search results - page 7 / 23 » Approximating Low Latency Queueing Buffer Latency |
ISCA
2002
IEEE
14 years 18 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
CF
2006
ACM
14 years 1 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
ISCA
1997
IEEE
13 years 12 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
TON
2008
13 years 7 months ago
2008
Scalability considerations drive the evolution of switch design from output queueing to input queueing and further to combined input and crosspoint queueing (CICQ). However, CICQ s...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
Processing-in-Memory (PIM) technology encompasses a range of research leveraging a tight coupling of memory and processing. The most unique features of the technology are extremel...