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» Arbitrary Bit Permutations in One or Two Cycles
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ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 12 days ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
SIROCCO
2010
13 years 8 months ago
Multipath Spanners
Abstract. This paper concerns graph spanners that approximate multipaths between pair of vertices of an undirected graphs with n vertices. Classically, a spanner H of stretch s for...
Cyril Gavoille, Quentin Godfroy, Laurent Viennot
AES
2000
Springer
117views Cryptology» more  AES 2000»
13 years 11 months ago
A Comparison of AES Candidates on the Alpha 21264
We compare the five candidates for the Advanced Encryption Standard based on their performance on the Alpha 21264, a 64-bit superscalar processor. There are several new features o...
Richard Weiss, Nathan L. Binkert
FOCS
2000
IEEE
13 years 11 months ago
Extracting Randomness via Repeated Condensing
Extractors (defined by Nisan and Zuckerman) are procedures that use a small number of truly random bits (called the seed) to extract many (almost) truly random bits from arbitrar...
Omer Reingold, Ronen Shaltiel, Avi Wigderson
RTCSA
2007
IEEE
14 years 1 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...