The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accurac...
Madhu Saravana Sibi Govindan, Stephen W. Keckler, ...
Creating a compelling haptic sense of immersion in a virtual environment is a challenging task for the control engineer. A haptic display must render both low impedance free-space...
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
We describe an approach to building security services for context-aware environments. Specifically, we focus on the design of security services that incorporate the use of securi...
Michael J. Covington, Prahlad Fogla, Zhiyuan Zhan,...