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SLIP
2003
ACM
14 years 1 months ago
A hierarchical three-way interconnect architecture for hexagonal processors
The problem of interconnect architecture arises when an array of processors needs to be integrated on one chip. With the deep sub-micron technology, devices become cheap while wir...
Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Che...
ISLPED
2009
ACM
110views Hardware» more  ISLPED 2009»
14 years 2 months ago
End-to-end validation of architectural power models
While researchers have invested substantial effort to build architectural power models, validating such models has proven difficult at best. In this paper, we examine the accurac...
Madhu Saravana Sibi Govindan, Stephen W. Keckler, ...
ICRA
2000
IEEE
121views Robotics» more  ICRA 2000»
14 years 4 days ago
Stable Haptic Interaction Using the Excalibur Force Display
Creating a compelling haptic sense of immersion in a virtual environment is a challenging task for the control engineer. A haptic display must render both low impedance free-space...
Richard J. Adams, Daniel Klowden, Blake Hannaford
DSD
2003
IEEE
138views Hardware» more  DSD 2003»
14 years 1 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ACSAC
2002
IEEE
14 years 22 days ago
A Context-Aware Security Architecture for Emerging Applications
We describe an approach to building security services for context-aware environments. Specifically, we focus on the design of security services that incorporate the use of securi...
Michael J. Covington, Prahlad Fogla, Zhiyuan Zhan,...