Sciweavers

294 search results - page 52 / 59
» Architectural Exploration and Optimization of Local Memory i...
Sort
View
ICPP
1999
IEEE
13 years 11 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
CHES
2009
Springer
230views Cryptology» more  CHES 2009»
14 years 7 months ago
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
David Kammler, Diandian Zhang, Dominik Auras, Gerd...
GCC
2004
Springer
14 years 14 days ago
Image-Based Walkthrough over Internet on Mobile Devices
Real-time rendering of complex 3D scene on mobile devices is a challenging task. The main reason is that mobile devices have limited computational capabilities and are lack of powe...
Yu Lei, Zhongding Jiang, Deren Chen, Hujun Bao
SPAA
1996
ACM
13 years 11 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
LCPC
2005
Springer
14 years 17 days ago
Manipulating MAXLIVE for Spill-Free Register Allocation
Abstract. Many embedded systems use single-chip microcontrollers which have no on-chip RAM. In such a system, the processor registers must hold all live data values. Nanocontroller...
Shashi Deepa Arcot, Henry G. Dietz, Sarojini Priya...