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MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
13 years 8 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
CGF
2010
105views more  CGF 2010»
13 years 8 months ago
Streaming-Enabled Parallel Dataflow Architecture for Multicore Systems
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...
ESTIMEDIA
2003
Springer
14 years 1 months ago
Perception Coprocessors for Embedded Systems
Recognizing speech, gestures, and visual features are important interface capabilities for embedded mobile systems. Perception algorithms have many traits in common with more conv...
Binu K. Mathew, Al Davis, Ali Ibrahim
ASAP
2006
IEEE
97views Hardware» more  ASAP 2006»
14 years 2 months ago
Dynamic-SIMD for lens distortion compensation
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Ba...
LCPC
2001
Springer
14 years 1 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann