This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed o...
Valavan Manohararajah, Stephen Dean Brown, Zvonko ...
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...