The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...