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RTAS
1997
IEEE
15 years 8 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
126
Voted
FPGA
2009
ACM
343views FPGA» more  FPGA 2009»
15 years 10 months ago
Fpga-based face detection system using Haar classifiers
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kas...
147
Voted
NOSSDAV
2005
Springer
15 years 9 months ago
MOPAR: a mobile peer-to-peer overlay architecture for interest management of massively multiplayer online games
In this paper we propose a fully distributed peer-to-peer (P2P) infrastructure supporting Networked Virtual Environment (NVE) applications, such as massively multiplayer online ga...
Anthony (Peiqun) Yu, Son T. Vuong
SIGCOMM
2009
ACM
15 years 10 months ago
BCube: a high performance, server-centric network architecture for modular data centers
This paper presents BCube, a new network architecture specifically designed for shipping-container based, modular data centers. At the core of the BCube architecture is its serve...
Chuanxiong Guo, Guohan Lu, Dan Li, Haitao Wu, Xuan...
SENSYS
2006
ACM
15 years 10 months ago
The tenet architecture for tiered sensor networks
Most sensor network research and software design has been guided by an architectural principle that permits multi-node data fusion on small-form-factor, resource-poor nodes, or mo...
Omprakash Gnawali, Ki-Young Jang, Jeongyeup Paek, ...