218 search results - page 13 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
VLSISP
2011
13 years 4 months ago
2011
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
ISCA
2002
IEEE
14 years 2 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
CODES
2006
IEEE
14 years 3 months ago
2006
IEEE
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...