218 search results - page 32 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
ICC
2007
IEEE
14 years 3 months ago
2007
IEEE
— Cognitive networks are the latest progression of cognitive functionality into the networking stack, an effort which began with a layer one and two focus on cognitive radios, an...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Previous studies have shown that wireless DSP algorithms exhibit high levels of data level parallelism (DLP). Commercial and research work in the field of software defined radio...
EMSOFT
2008
Springer
13 years 10 months ago
2008
Springer
In this paper we present a design space exploration flow to achieve energy efficiency for streaming applications on MPSoCs while meeting the specified throughput constraints. The ...
FPL
2007
Springer
14 years 3 months ago
2007
Springer
Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and progr...