218 search results - page 33 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
DATE
2003
IEEE
14 years 2 months ago
2003
IEEE
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
FPGA
2008
ACM
13 years 10 months ago
2008
ACM
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
CORR
2006
Springer
13 years 9 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
DAC
2005
ACM
13 years 11 months ago
2005
ACM
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns [6,7] can provide significant advantages in terms of manufacturability and de...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...