218 search results - page 9 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
SBCCI
2009
ACM
14 years 3 months ago
2009
ACM
The purpose of this work is the proposal of a 10-Bit / 1 MSPS Analog to Digital Converter (ADC) with error correction to match the requirements of a CMOS wavefront sensor for opht...
ERSA
2004
13 years 10 months ago
2004
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipeline...
TVLSI
2008
13 years 9 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...