1381 search results - page 101 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ICASSP
2011
IEEE
12 years 12 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
ANCS
2007
ACM
14 years 7 days ago
2007
ACM
There is a growing interest in designing high-performance network devices to perform packet processing at flow level. Applications such as stateful access control, deep inspection...
ISCAPDCS
2004
13 years 9 months ago
2004
Increasing multimedia applications such as teleconferencing and video-on-demand require the Internet to effectively provide high-performance multicast support. One of the promisin...
CF
2005
ACM
13 years 10 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...