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JCM
2008
63views more  JCM 2008»
13 years 8 months ago
A Node Encoding of Torus Topology and Its Improved Routing Algorithm
With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the perf...
Xiaoqiang Yang, Junmin Li, Huimin Du, Jungang Han
MSS
2003
IEEE
76views Hardware» more  MSS 2003»
14 years 1 months ago
A Scalable Architecture for Clustered Network Attached Storage
Network attached storage systems must provide highly available access to data while maintaining high performance, easy management, and maximum scalability. In this paper, we descr...
Jonathan D. Bright, John A. Chandy
ISVLSI
2005
IEEE
80views VLSI» more  ISVLSI 2005»
14 years 1 months ago
Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs
Mesh interconnect can be efficiently utilized while tree networks encourage the short routing distances. In this paper, we present the property analysis of a cluster-based interc...
Renqiu Huang, Ranga Vemuri
IPPS
1997
IEEE
14 years 14 days ago
An Architecture Workbench for Multicomputers
The large design space of modern computer architectures calls for performance modelling tools to facilitate the evaluation of different alternatives. In this paper, we give an ove...
Andy D. Pimentel, Louis O. Hertzberger
CODES
2006
IEEE
14 years 2 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...