1381 search results - page 111 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DAC
2007
ACM
14 years 10 months ago
2007
ACM
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
ICCAD
2007
IEEE
14 years 6 months ago
2007
IEEE
Abstract— This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficient...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...